LPC2929FBD144,551

The LPC2929FBD144,551 is an ARM9 microcontroller based on ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125MHz. The device incorporates full-speed USB 2.0 OTG and device controller, CAN and LIN, 56kB SRAM, up to 768kB flash memory, external memory interface, three 10-bit ADCs and multiple serial and parallel interfaces in a single. To optimize system power consumption the device has a very flexible clock generation unit (CGU) that provides dynamic clock gating and scaling.

• Multi-layer AHB system bus at 125MHz with four separate layers
• External static memory controller (SMC)
• USB 2.0 full-speed device/OTG controller with dedicated DMA controller and on-chip device PHY
• Two-channel CAN controller supporting FullCAN and extensive message filtering
• Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support and RS485/EIA-485 (9-bit) support
• Two I2C-bus interfaces
• Multiple trigger-start option for all ADCs - timer, PWM, other ADC and external signal input
• Four 32-bit timers each containing four capture-and-compare registers linked to I/Os
• Four 6-channel PWMs with capture and trap functionality
• Two dedicated 32-bit timers to schedule and synchronize PWM and ADC
• Up to 104 general-purpose I/O pins with programmable pull-up, pull-down or bus keeper
• Vectored interrupt controller (VIC) with 16 priority levels
• Up to 21 level-sensitive external interrupt pins, including USB, CAN and LIN wake-up features
• Configurable clock-out pin for driving external system clocks
• Processor wake-up from power-down via external interrupt pins; CAN or LIN activity
• Flexible reset generator unit (RGU) able to control resets of individual modules
• Flexible clock-generation unit (CGU0) able to control clock frequency of individual modules
• Second CGU (CGU1) with its own PLL generates USB clocks and a configurable clock output
• Highly configurable system power management unit (PMU)
• Standard ARM test and debug interface with real-time in-circuit emulator
• Boundary-scan test supported
• ETM/ETB debug functions with 8 kB of dedicated SRAM